Job Responsibilityo Good knowledge in full custom and semi-custom flows, fundamentals of CMOS Transistors
o Good knowledge in analog circuit design and analog layout using Cadence tools
o Experience in characterizing devices in 65nm and 28nm process technologies
o Good knowledge in the concepts of Analog to Digital Converter
o Experience in designing supply independent biasing, bandgap reference design (SMIC130nm, TSMC 65nm and 28nm), non-over-lap clock generator, LDO regulator
o Experience in reliability verification flows like Aging, SCARF, Burn-in, EOS and RV
o Exposure to the MSV tool flows in Cadence
o Experience in leading team
o Experience in creating micro architecture from functional specifications, RTL design and Logic Synthesis, Static Timing Analysis and good in technical documentation
Job RequirementsJob Benifits
